Power consumption in network switching chips is increasing as workloads increase. To handle additional packets, the switching chips may use faster clock frequencies in order to process the packets. Dynamic power consumption is proportional to the clock frequency as well as the switching activities of the circuit. Thus, as clock frequency increases, the power consumption of the chip does as well. Therefore, reducing the frequency of the clock signal or signals in a manner that avoids dropping data packets may reduce the power consumed by the chip without sacrificing performance.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.